The invention relates to a semiconductor device including a MIS transistor in which metal suicide layers are selectively formed on a surface of a gate electrode and on a surface of the portion of the semiconductor substrate to be a high concentration impurity region, and relates to a manufacturing method of the device.
In the manufacturing of semiconductor devices in recent years, a salicide-forming technology has been used for lowering the resistance of gate electrodes, source electrodes or drain electrodes, in which technology metal suicide films are formed on each electrode at the same time by the reaction of silicon constituting each electrode and a refractory metal material such as Ti, Co, or Ni.
Further, in the actual manufacturing of semiconductor devices, in order to increase resistance to electrostatic discharge puncture caused by ESD (Electro-Static Discharge) and the like, a resistance element connected in series with the transistor has been provided by not forming silicide in a portion of the source region and drain region.
FIGS. 19A to C and FIGS. 20A to C are cross-sectional views for showing each step in a method for manufacturing a semiconductor device according to a first conventional example, specifically a method for manufacturing a MIS type transistor in which a silicide region and a non-silicide region are separately formed.
First, as shown in FIG. 19A, an input/output transistor-forming region rA and an internal transistor-forming region rB are partitioned by forming an isolation insulating film 11 in a p-type silicon substrate 10. After that, a first gate electrode 13a of an n-type polycrystalline silicon film is formed above the input/output transistor-forming region rA with a first gate insulating film 12a interposed between the first gate electrode 13a and the input/output transistor-forming region rA. Further, a second gate electrode 13b of an n-type polycrystalline silicon film is formed above the internal transistor-forming region rB with a second gate insulating film 12b interposed between the second gate electrode 13b and the internal transistor-forming region rB. Thereafter, by using the first gate electrode 13a as a mask, ion implantation is performed on the input/output transistor-forming region rA, thereby forming a first n-type low concentration impurity region 14a. Also, by using the second gate electrode 13b as a mask, ion implantation is performed on the inner transistor-forming region rB, thereby forming a second n-type low concentration impurity region 14b. After that, first sidewall insulating films 15a are formed on the side surfaces of the first gate electrode 13a and, at the same time, second side-wall insulating films 15b are formed on the side surfaces of the second gate electrode 13b. Thereafter, by using the first gate electrode 13a and the first sidewall insulating films 15a as a mask, ion implantation is performed on the input/output transistor-forming region rA, thereby forming n-type high concentration impurity regions 16a to configure a source region and a drain region. Also, by using the second gate electrode 13b and the second sidewall insulating films 15b as a mask, ion implantation is performed on the internal transistor-forming region rB, thereby forming second high concentration impurity regions 16b to configure a source region and a drain region.
Next, as shown in FIG. 19B, a silicon oxide film 17 is deposited all over the semiconductor substrate 10. Thereafter, as shown in FIG. 19C, by using a resist pattern 18 as a mask covering a non-silicide region in which silicide is not provided (the first gate electrode 13a, first sidewall insulating film 15a, and the portion of the first high concentration impurity region 16a located in proximity to the first low concentration impurity region 14a), wet etching is performed on the silicon oxide film 17.
Then, after the resist pattern 18 is removed, a refractory metal film 19 is deposited all over the semiconductor substrate 10 as shown in FIG. 20A. Thereafter, as shown in FIG. 20B, by using the isolation insulating film 11, the second sidewall insulating film 15b, and the residual silicon oxide film 17 still remaining on the non-silicide region as a mask, heat treatment is applied on the semiconductor substrate 10. Thereby, first refractory metal suicide films 20a are selectively formed on the surfaces of the first high concentration impurity regions 16a except for their portions located underneath the residual silicon oxide film 17. Also, a second refractory metal silicide film 20b is selectively formed on each surface of the second gate electrode 13b and the second high concentration impurity region 16b. After that, the unreacted refractory metal film 19 is removed by wet etching using an etching solution including H2SO4 and H2O2, etc.
Next, as shown in FIG. 20C, after the formation of an inter-layer insulating film 21 all over the semiconductor substrate 10, a first contact 22a connecting to the first high concentration impurity region 16a through the refractory metal silicide film 20a and a second contact 22b connecting to the second high concentration impurity region 16b through the second refractory metal silicide film 20b are formed in the inter-layer insulating film 21. Thereafter, a first metal wiring line 23a connecting to the first contact 22a and a second metal wiring line 23b connecting to the second contact 22b are formed on the inter-layer insulating film 21. This completes the manufacturing of the MIS transistors in which the silicide region and the non-silicide region are separately manufactured.
However, the first conventional example has a problem that the gate resistance of the input/output transistor is increased because silicide is not formed also on the first gate electrode 13a. 
By the way, the official gazette of Japanese Patent Laid-Open No. 11-126900 (hereinafter, referred to as a second conventional example) discloses a method for forming a second sidewall insulating film on the side surface of a gate electrode of an input/output transistor with a first sidewall insulating film interposed between the second sidewall insulating film and the gate electrode, thereby preventing a metal silicide layer from being formed on regions located underneath the second sidewall insulating films in the surfaces of high concentration impurity regions to configure the source region and drain region of the input/output transistor. However, according to the second conventional example, in the internal transistor-forming region, a metal suicide layer is formed not only on the surfaces of the high concentration impurity regions to configure the source region and drain region, but also the metal silicide layer is formed on the surfaces of low concentration impurity regions having a shallow junction depth. This results in a problem of an increased junction leakage current.